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128k x 32 synchronous-pipelined ram cy7c1340a/ gvt71128c32 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-05153 rev. *b revised january 19, 2003 features ? fast access times: 5, 6, and 7 ns fast clock speed: 100, 83, and 66 mhz provides high performance 3-1-1-1 access rate fast oe access times: 5, 6, and 7 ns optimal for performance (two-cycle chip deselect, depth expansion without wait state) single +3.3v ?5% and +10%power supply supports +2.5v i/o 5v tolerant inputs except i/os clamp diodes to v ssq at all outputs common data inputs and outputs byte write enable and global write control three chip enables for depth expansion and address pipeline address, control, input, and output pipeline registers internally self-timed write cycle burst control pins (interleaved or linear burst sequence) automatic power-down for portable applications high-density, high-speed packages low-capacitive bus loading high 30-pf output drive capability at rated access time functional description the cypress synchronous burst sram family employs high-speed, low-power cmos designs using advanced triple-layer polysilicon, double-layer metal technology. each memory cell consists of four transistors and two high valued resistors. the cy7c1340a/gvt71128c32 sram integrates 131,072 32 sram cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (ce ), depth-expansion chip enables (ce2 and ce2), burst control inputs (adsc , adsp , and adv ), write enables (bw1 , bw2 , bw3 , bw4 , and bwe ), and global write (gw ). asynchronous inputs include the output enable (oe ) and burst mode control (mode). the data outputs (q), enabled by oe , are also asynchronous. addresses and chip enables are registered with either address status processor (adsp ) or address status controller (adsc ) input pins. subsequent burst addresses can be internally generated as controlled by the burst advance pin (adv ). address, data inputs, and write controls are registered on-chip to initiate self-timed write cycle. write cycles can be one to four bytes wide as controlled by the write control inputs. individual byte write allows individual byte to be written. bw1 controls dq1 ? dq8. bw2 controls dq9 ? dq16. bw3 controls dq17 ? dq24. bw4 controls dq25 ? dq32. bw1 , bw2 , bw3 , and bw4 can be active only with bwe being low. gw being low causes all bytes to be written. this device also incorpo- rates pipelined enable circuit for easy depth expansion without penalizing system performance. the cy7c1340a/gvt71128c32 operates from a +3.3v power supply. all inputs and outputs are ttl-compatible. the device is ideally suited for 486, pentium ? , 680 0, and powerpc ? systems and for systems that benefit from a wide synchronous data bus. selection guide 7c1340a-100 71128c36-5 7c1340a-83 71128c36-6 7c1340a-66 71128c36-7 unit maximum access time 5 6 7 ns maximum operating current 225 185 120 ma maximum cmos standby current 2 2 2 ma
cy7c1340a/ gvt71128c32 document #: 38-05153 rev. *b page 2 of 12 note: 1. the functional block diagram illustrates simplified device operation. see truth table, pin descriptions, and timing diagrams for detailed information. functional block diagram [1] dq dq bw3# bwe# bw4# ce# ce2 ce2# byte 3 write byte 4 write output register oe# byte 3 write adsp# adsc# address register binary counter & logic clr a16-a2 a1-a0 adv# mode 128k x 8 x 4 sram array output buffers input register byte 4 write dq1- dq32 dq dq dq bw1# bw2# gw# byte 1 write byte 2 write clk byte 2 write byte 1 write dq dq enable power down logic zz
cy7c1340a/ gvt71128c32 document #: 38-05153 rev. *b page 3 of 12 pin configuration a5 a4 a3 a2 a1 a0 nc nc v ss v cc nc a10 a11 a12 a13 a14 nc dq16 dq15 v ccq v ssq dq14 dq13 dq12 dq11 v ssq v ccq dq10 dq9 v ss nc v cc dq8 dq7 v ccq v ssq dq6 dq5 dq4 dq3 v ssq v ccq dq2 dq1 nc nc dq17 dq18 v ccq v ssq dq19 dq20 dq21 dq22 v ssq v ccq nc v cc nc v ss v ccq v ssq dq30 v ssq v ccq dq31 dq32 nc a6 a7 ce ce2 bw4 bw3 bw2 bw1 ce 2 v cc v ss clk gw bwe oe adsp a8 a9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a15 adv adsc zz nc mode a16 100-pin tqfp cy7c1340a top view dq23 dq24 dq25 dq26 dq28 dq29 dq27
cy7c1340a/ gvt71128c32 document #: 38-05153 rev. *b page 4 of 12 pin descriptions name type description a0 ? a16 input- synchronous addresses : these inputs are registered and must meet the set-up and hold times around the rising edge of clk. the burst counter generates internal addresses associated with a0 and a1, during burst cycle and wait cycle. bw1 , bw2 , bw3 , bw4 input- synchronous byte write : a byte write is low for a write cycle and high for a read cycle. bw1 controls dq1 ? dq8. bw2 controls dq9 ? dq16. bw3 controls dq17 ? dq24. bw4 controls dq25 ? dq32. data i/o are high-impedance if either of these inputs are low, conditioned by bwe being low. bwe input- synchronous write enable : this active low input gates byte write operations and must meet the set-up and hold times around the rising edge of clk. gw input- synchronous global write : this active low input allows a full 32-bit write to occur independent of the bwe and bwn lines and must meet the set-up and hold times around the rising edge of clk. clk input- synchronous clock : this signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge. all synchronous inputs must meet set-up and hold times around the clock ? s rising edge. ce input- synchronous chip enable : this active low input is used to enable the device and to gate adsp . ce2 input- synchronous chip enable : this active low input is used to enable the device. ce2 input- synchronous chip enable : this active high input is used to enable the device. oe input output enable : this active low asynchronous input enables the data output drivers. adv input- synchronous address advance : this active low input is used to control the internal burst counter. a high on this pin generates wait cycle (no address advance). adsp input- synchronous address status processor : this active low input, along with ce being low, causes a new external address to be registered and a read cycle is initiated using the new address. adsc input- synchronous address status controller : this active low input causes device to be de-selected or selected along with new external address to be registered. a read or write cycle is initiated depending upon write control inputs. mode input- static mode : this input selects the burst sequence. a low on this pin selects linear burst. a nc or high on this pin selects interleaved burst. zz input- asynchronous snooze : this active high input puts the device in low power consumption standby mode. for normal operation, this input has to be either low or nc (no connect). dq1 ? dq32 input/ output data inputs/outputs : first byte is dq1 ? dq8. second byte is dq9 ? dq16. third byte is dq17 ? dq24. fourth byte is dq25 ? dq32. input data must meet set-up and hold times around the rising edge of clk. v cc supply power supply : +3.3v ? 5% to +10%. pin 14 does not have to be connected directly to v cc as long as it is greater than v ih . v ss ground ground : gnd v ccq i/o supply output buffer supply : +3.3v ? 5% to +10%. for 2.5v i/o: 2.375v to v cc . v ssq i/o ground output buffer ground : gnd nc - no connect : these signals are not internally connected. burst address table (mode = nc/v cc ) first address (external) second address (internal) third address (internal) fourth address (internal) a...a00 a...a01 a...a10 a...a11 a...a01 a...a00 a...a11 a...a10 a...a10 a...a11 a...a00 a...a01 a...a11 a...a10 a...a01 a...a00 burst address table (mode = gnd) first address (external) second address (internal) third address (internal) fourth address (internal) a...a00 a...a01 a...a10 a...a11 a...a01 a...a10 a...a11 a...a00 a...a10 a...a11 a...a00 a...a01 a...a11 a...a00 a...a01 a...a10
cy7c1340a/ gvt71128c32 document #: 38-05153 rev. *b page 5 of 12 truth table [2, 3, 4, 5, 6, 7, 8] operation address used ce ce2 ce2 adsp adsc adv write oe clk dq deselected cycle, power down none h x x x l x x x l ? hhigh-z deselected cycle, power down none l x l l x x x x l ? hhigh-z deselected cycle, power down none l h x l x x x x l ? hhigh-z deselected cycle, power down none l x l h l x x x l ? hhigh-z deselected cycle, power down none l h x h l x x x l ? hhigh-z read cycle, begin burst external l l h l x x x l l ? hq read cycle, begin burst external l l h l x x x h l ? hhigh-z write cycle, begin burst external l l h h l x l x l ? hd read cycle, begin burst external l l h h l x h l l ? hq read cycle, begin burst external l l h h l x h h l ? hhigh-z read cycle, continue burst next x x x h h l h l l ? hq read cycle, continue burst next x x x h h l h h l ? hhigh-z read cycle, continue burst next h x x x h l h l l ? hq read cycle, continue burst next h x x x h l h h l ? hhigh-z write cycle, continue burst next x x x h h l l x l ? hd write cycle, continue burst next h x x x h l l x l ? hd read cycle, suspend burst current x x x h h h h l l ? hq read cycle, suspend burst current x x x h h h h h l ? hhigh-z read cycle, suspend burst current h x x x h h h l l ? hq read cycle, suspend burst current h x x x h h h h l ? hhigh-z write cycle, suspend burst current x x x h h h l x l ? hd write cycle, suspend burst current h x x x h h l x l ? hd partial truth table for read/write function gw bwe bw1 bw2 bw3 bw4 read hhxxxx read h l h h h h write one byte h l l h h h write all bytes h l l l l l write all bytes l x x x x x notes: 2. x means ? don ? t care. ? h means logic high. l means logic low. write = l means [bwe + bw1 *bw2 *bw3 *bw4 ]*gw equals low. write = h means [bwe + bw1 *bw2 *bw3 *bw4 ]*gw equals high. 3. bw1 enables write to dq1 ? dq8. bw2 enables write to dq9 ? dq16. bw3 enables write to dq17 ? dq24. bw4 enables write to dq25 ? dq32. 4. all inputs except oe must meet set-up and hold times around the rising edge (low ? high) of clk. 5. suspending burst generates wait cycle. 6. for a write operation following a read operation, oe must be high before the input data required set-up time plus high-z time for oe and staying high throughout the input data hold time. 7. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 8. adsp low along with chip being selected always initiates a read cycle at the l ? h edge of clk. a write cycle can be performed by setting write low for the clk l ? h edge of the subsequent wait cycle. refer to write timing diagram for clarification.
cy7c1340a/ gvt71128c32 document #: 38-05153 rev. *b page 6 of 12 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) voltage on v cc supply relative to v ss ......... ? 0.5v to +4.6v v in ........................................................... ? 0.5v to v cc +0.5v storage temperature (plastic) .................... ? 55 c to +150 c junction temperature ............................................... +150 c power dissipation.......................................................... 1.0w short circuit output current ........................................ 50 ma operating range range ambient temperature [9] v dd [10,11] commercial 0 c to +70 c 3.3v ? 5% / +10% industrial ? 40 c to +85 c electrical characteristics over the operating range parameter description test conditions min. max. unit v ihd input high (logic 1) voltage [12, 13] data inputs (dqxx) 2.0 v ccq + 0.3 v v ih all other inputs 2.0 4.6 v v il input low (logic 0) voltage [12, 13] ? 0.3 0.8 v il i input leakage current [14] 0v < v in < v cc ? 2 2 a il o output leakage current output(s) disabled, 0v < v out < v cc ? 2 2 a v oh output high voltage [12, 15] i oh = ? 4.0 ma 2.4 v v ol output low voltage [12, 15] i ol = 8.0 ma 0.4 v v cc supply voltage [12] 3.1 3.6 v v ccq i/o supply voltage (3.3v i/o) [12] 3.1 3.6 v v ccq i/o supply voltage (2.5v i/o) [12] 2.375 v cc parameter description conditions typ. -5 -6 -7 unit i cc power supply current: operating [16, 17, 18] device selected; all inputs < v il or > v ih ; cycle time > t kc min.; v cc = max.; outputs open 80 225 185 120 ma i sb2 cmos standby [17, 18] device deselected; v cc = max.; all inputs < v ss + 0.2 or > v cc ? 0.2; all inputs static; clk frequency = 0 0.2 2 2 2 ma i sb3 ttl standby [17, 18] device deselected; all inputs < v il or > v ih ; all inputs static; v cc = max.; clk frequency = 0 8 181818ma i sb4 clock running [17, 18] device deselected; all inputs < v il or > v ih ; v cc = max.; clk cycle time > t kc min. 12 30 25 20 ma capacitance [19] parameter description test conditions typ. max. unit c i input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 3 4 pf c o input/output capacitance (dq) 6 7 pf notes: 9. t a is the case temperature 10. please refer to waveform (d). 11. power supply ramp-up should be monotonic. 12. all voltages referenced to v ss (gnd). 13. overshoot: v ih +6.0v for t t kc /2. undershoot: v il ? 2.0v for t t kc /2. 14. mode pin has an internal pull-up and zz pin has an internal pull-down. these two pins exhibit an input leakage current of 3 0 a. 15. ac i/o curves are available upon request. 16. i cc is given with no output current. i cc increases with greater output loading and faster cycle times. 17. ? device deselected ? means the device is in power-down mode as defined in the truth table. ? device selected ? means the device is active. 18. typical values are measured at 3.3v, 25 c, and 8.5-ns cycle time. 19. this parameter is sampled.
cy7c1340a/ gvt71128c32 document #: 38-05153 rev. *b page 7 of 12 capacitance derating [20] parameter description typ. max. unit ? t kq clock to output valid 0.016 ns / pf thermal resistance description test conditions symbol tqfp typ. unit thermal resistance (junction to ambient) still air, soldered on a 4.25 1.125 inch, four-layer pcb ja 20 c/w thermal resistance (junction to case) jc 1 c/w ac test loads and waveforms ? 3.3v i/o [21] dq 317 ? 351 ? 5pf (a) (b) dq 50 ? z 0 = 50 ? v t = 1.5v 3.3v all input pulses 3.0v 0v 90% 10% 90% 10% 1.5 ns 1.5 ns (c) 30 pf vddmin vddtyp tpu = 200us for proper reset bring vdd down to 0v (d) ac test loads and waveforms ? 2.5v i/o (a) dq 50 ? z 0 = 50 ? v t = 1.25v all input pulses 2.5v 0v 90% 10% 90% 10% 18 ns 1.8 ns (c) switching characteristics over the operating range [22] parameter description -5 100 mhz -6 83 mhz -7 66 mhz unit min. max. min. max. min. max. clock t kc clock cycle time 10 12 15 ns t kh clock high time 4 4 5 ns t kl clock low time 4 4 5 ns notes: 20. capacitance derating applies to capacitance different from the load capacitance shown in ac test loads for 3.3v or 2.5v i/o. 21. overshoot: vih(ac) cy7c1340a/ gvt71128c32 document #: 38-05153 rev. *b page 8 of 12 output times t kq clock to output valid 5 6 7 ns t kqx clock to output invalid 2 2 2 ns t kqlz clock to output in low-z [23, 24] 3 3 3 ns t kqhz clock to output in high-z [23, 24] 5 5 6 ns t oeq oe to output valid [25] 5 6 7 ns t oelz oe to output in low-z [23, 24] 0 0 0 ns t oehz oe to output in high-z [23, 24] 4 5 6 ns set-up times t s address, controls, and data in [26] 2.5 2.5 2.5 ns hold times t h address, controls, and data in [26] 0.5 0.5 0.5 ns switching waveforms read timing [27] notes: 23. output loading is specified with c l = 5 pf as in part (b) of ac test loads. 24. at any given temperature and voltage condition, t kqhz is less than t kqlz and t oehz is less than t oelz . 25. oe is a ? don ? t care ? when a byte write enable is sampled low. 26. this is a synchronous device. all synchronous inputs must meet specified set-up and hold time, except for ? don ? t care ? as defined in the truth table. 27. ce active in this timing diagram means that all chip enables ce , ce2, and ce2 are active. switching characteristics over the operating range [22] parameter description -5 100 mhz -6 83 mhz -7 66 mhz unit min. max. min. max. min. max. clk adsp# adsc# address bw1#, bw2#, bw3#, bw4#, bwe#, gw# ce# adv# oe# dq a1 a2 q(a1) q(a2) q(a2+1) q(a2+2) q(a2+3) q(a2) q(a2+1) t kq t kqlz t oelz t kq t s t h t kh t kl t kc t oeq single read burst read t h t h t s t s t s
cy7c1340a/ gvt71128c32 document #: 38-05153 rev. *b page 9 of 12 write timing [27] switching waveforms (continued) clk adsp# adsc# address ce# adv# oe# dq a1 a2 d(a2) d(a2+2) d(a2+3) d(a3) d(a3+1) d(a3+2) t s t h gw# a3 d(a1) d(a2+1) t kqx t oehz q d(a2+1) single write burst write burst write t h t h t s t s bw1#, bw2#, bw3#, bw4#, bwe#
cy7c1340a/ gvt71128c32 document #: 38-05153 rev. *b page 10 of 12 read/write timing [27] switching waveforms (continued) clk adsp# adsc# address ce# adv# oe# dq a1 a2 a3 q(a1) q(a2) t s t h t s t h a4 d(a3) q(a4) q(a4+1) q(a4+2) d(a5) d(a5+1) single write burst read burst write single reads a5 bw1#, bw2#, bw3#, bw4#, bwe#, gw# ordering information speed (mhz) ordering code package name package type operating range 100 cy7c1340a-100ac/ gvt71128c32t-5 a101 100-lead 14 20 1.4 mm thin quad flat pack commercial 83 cy7c1340a-83ac/ gvt71128c32t-6 a101 100-lead 14 20 1.4 mm thin quad flat pack 66 cy7c1340af-66ac/ gvt71128c32t-7 a101 100-lead 14 20 1.4 mm thin quad flat pack 66 CY7C1340AF-66AI/ gvt71128c32t-7i a101 100-lead 14 20 1.4 mm thin quad flat pack industrial 83 cy7c1340a-83ai/ gvt71128c32t-6i a101 100-lead 14 20 1.4 mm thin quad flat pack
cy7c1340a/ gvt71128c32 document #: 38-05153 rev. *b page 11 of 12 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. pentium is a registered trademark of intel corporation. powerpc is a trademark of ibm corporation. all products and company names mentioned in this document are the trademarks of their respective holders. package diagrams 100-pin thin plastic quad flatpack (14 20 1.4 mm) a101 51-85050-a
cy7c1340a/ gvt71128c32 document #: 38-05153 rev. *b page 12 of 12 document title: cy7c1340a/gvt71128c32 128k 32 synchronous-pipelined ram document number: 38-05153 rev. ecn no. issue date orig. of change description of change ** 109897 09/22/01 szv change from spec number: 38-01003 to 38-05153 *a 111530 02/06/02 glc add industrial temp to data sheet *b 123139 01/19/03 rbi add power up requirements to operating conditions information.

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